ADVANCED DIGITAL ELECTRONICS

     Digital Concepts and Number Systems and Principles of
     Combinational Logic Circuits.
     Analysis and Design of Combinational Logics.
     Principles of Sequential Logic Circuits, Counters & Registers.
     Design of Sequential Circuits.
     Introduction Programmable Logic Devices (PLDS).
     Introduction to FPGAs and ASIC Design.
     Introduction to CMOS Circuits.

VHDL LANGUAGE

     Introduction to VLSI Technology
     Identifiers and Literals
     Entities and Architectures
     Packages and Libraries
     Standard Package
     Std_logic_1164 Package
     Textio Package
     Other Packages
     Creating Packages
     Interface Declarations
     Port Declarations
     Generics
     Type Declarations
     Other Declarations
     Objects Declarations
     Subprogram Declarations
     Alias and Attribute Declarations
     Predefined Attribute
     Sequential Statements
     Wait Statements
     Assertion and Reports Statements
     Assignment Statements
     Procedure Call
     If Statement
     Case Statement
     Other Sequential Control Statements
     Operators
     Arithmetic
     IEEE Synthesis Packages
     Concurrent Statements
     Block Statement
     Process Statement
     Concurrent Procedure Call
     Concurrent Signal Assignments
     Concurrent Assertion Statement
     Component Instantiation
     General Statement
     Execution
     Configuration and Specifications
     Packages
     Writing Test benches

VERILOG HDL LANGUAGE

     Basics of the Verilog Language
     Verilog logic Value
     Verilog Data Types
     Other Wire Types
     Numbers
     Negative Numbers
     Strings
     Operators
     Arithmetic
     Hierarchy
     Procedures and Assignments
     Continuous Assignments statements
     Sequential Block
     Procedure Assignments
     Timing Controls and Delay
     Timing Control
     Data Slip
     Wait Statements
     Blocking and Non Blocking Assignments
     Procedural Continuous Assignments
     Task and Functions
     Control Statements
     Case and If Statements
     Loop Statement
     Disable
     Fork and Join
     Logic –Gate Modeling
     Built in logic Models
     User Defined Primitives
     Modeling Delay
     Net and Gate Delay
     Pin-to-Pin Delay
     Altering Parameters
     Other Verilog Features
     Display Tasks
     File I/O Tasks
     Timescale, Simulation, and Timing-Check Tasks
     PLA Tasks
     Stochastic Analysis Tasks
     Simulation Time Functions
     Conversion Functions
     Probability Distribution Functions
     Programming Language Interface
     Writing Test benches

ADVANCED LOGIC SYNTHESIS USING FPGA
  CMOS LOGIC

       Introduction
       Semiconductor device Physics
       Fabrication of MOSFET
       MOSFET operation and modeling
       MOS inverters - Static characteristics
       MOS inverters - Switching characteristics and interconnect effects.

  FIELD PROGRAMMABLE GATE ARRAYS (FPGAs)

       Introduction to Programmable Logic devices &FPGAs, and Programming
       Technologies
       FPGA Design Flow
       Technology Mapping, Placement & Routing
       FPGA Architectures: Introduction to Xilinx devices, SPARTAN II
       Xilinx Design Flow and Implementation Details, Applications and Case Study on FPGAs